Vendor: Synopsys, Inc. Category: PVT Monitor

PVT Controller (Series 4), TSMC N7

The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-Syste…

TSMC 7nm N7 Available on request View all specifications

Overview

The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-System used to increase System on Chip performance and reliability. On-chip PVT monitoring is now a key consideration for 28-nanometer (nm) and FinFET technology based designs. This In-Chip Sensing and PVT Monitoring IP is available as part of the Synopsys DesignWare® Foundation IP portfolio. It also forms the foundation of the new Synopsys Silicon Lifecycle Management (SLM) platform. SLM enables new levels of insight for both SoC providers as well as their customers to optimize operational activities at each stage of the device and system lifecycles from design to in-field.

Key features

  • Monitor multiple instances of Process Monitors, Voltage Monitors & Temperature Sensors
  • Temperature & Voltage Alarms / Hard Stops
  • PVT Statistics (max min sample values, sample counters)
  • Clock synth
  • Auto-polling
  • Soft and hard lock of register access
  • iJTAG access support

Benefits

  • Relieves system controller of many sensor related housekeeping tasks
  • Provides a standard digital interface for the system controller to the PVT sensors
  • Continuously monitors voltage and temperature levels and triggers alarms
  • Clock Speed Optimization
  • Increased Reliability & Device Lifetime

Applications

  • Thermal monitoring and management
  • Power and energy optimization
  • Process speed assessment
  • Enhancing reliability

What’s Included?

  • Datasheet
  • RTL & Constraints (PVT-Controller)
  • Verilog model

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7 Available on request

Specifications

Identity

Part Number
dwc_sensors_pvt_c_series3p_tsmcn7
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

Learn more about PVT Monitor IP core

Developing Assertion IP for Formal Verification

Assertion language provides a way to express the properties and constraints for property based formal verification environment. Current assertion languages such as SVA and PSL offer a great set of constructs that enables one to write assertions in number of ways. his paper covers certain coding guidelines which should be considered while developing a formal friendly assertion based IP.

Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study

This paper discusses about the intelligent low power techniques such as context based clock gating and how they are useful for IoT applications. It also describes how it improves the overall power efficiency of the system. The power statistics shared shows how the overall idle power and functional power consumption is significantly reduced. Further we discuss about how it can be combined with few other low power techniques to reduce the overall power

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

A New Methodology for Hardware Software Co-verification

Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers require these tools and software and it would be an expensive proposition for IP developers.

Frequently asked questions about PVT Monitor IP cores

What is PVT Controller (Series 4), TSMC N7?

PVT Controller (Series 4), TSMC N7 is a PVT Monitor IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this PVT Monitor?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PVT Monitor IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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