What is Programmable 9-bit CMOS low-frequency divider (5...511 dividing ratio)?
Programmable 9-bit CMOS low-frequency divider (5...511 dividing ratio) is a Clock Generator IP core from NTLab listed on Semi IP Hub.
Vendor:
NTLab
Category:
Clock Generator
Programmable 9-bit CMOS low-frequency divider (5...511 dividing ratio)
The programmable CMOS low-frequency divider design is based on the 9-bit counter.
Overview
The programmable CMOS low-frequency divider design is based on the 9-bit counter. Since this structure consists of the static triggers, current consumption is closed to zero when there is no input clock. The dividing ratio is 5...511.
Input frequency is 26...300 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Key features
- iHP SGB25V
- Dividing ratio: 5…511
- Compact structure
- Portable to other technologies (upon request)
Block Diagram
250iHP_RDIV_01 block diagram
Applications
- PLL frequency synthesizer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Specifications
Identity
Part Number
250iHP_RDIV_01
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Frequently asked questions about Clock Generator IP cores
How should engineers evaluate this Clock Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.