What is Programmable 5-bit CMOS low-frequency divider?
Programmable 5-bit CMOS low-frequency divider is a Clock Generator IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
NTLab
Category:
Clock Generator
Programmable 5-bit CMOS low-frequency divider
The programmable CMOS low-frequency divider configuration of asynchronous programmable impulse counter, control logic and output …
Overview
The programmable CMOS low-frequency divider configuration of asynchronous programmable impulse counter, control logic and output buffer.
The block is fabricated on TSMC SiGe BiCMOS 0.18 um.
Key features
- TSMC SiGe BiCMOS 0.18 um
- Range of division ratio from 1 to 31
- Low current consumption 10 uA
- Portable to other technologies (upon request)
Block Diagram
180TSMC_RDIV_03 block diagram
Applications
- PLL frequency synthesizer
What’s Included?
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Verilog behavior model
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
Specifications
Identity
Part Number
180TSMC_RDIV_03
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Frequently asked questions about Clock Generator IP cores
How should engineers evaluate this Clock Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.