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Rohan Bhatnagar, Staff Product Manager, Synopsys EDA Group
Assertion language provides a way to express the properties and constraints for property based formal verification environment. Current assertion languages such as SVA and PSL offer a great set of constructs that enables one to write assertions in number of ways. his paper covers certain coding guidelines which should be considered while developing a formal friendly assertion based IP.
This paper discusses about the intelligent low power techniques such as context based clock gating and how they are useful for IoT applications. It also describes how it improves the overall power efficiency of the system. The power statistics shared shows how the overall idle power and functional power consumption is significantly reduced. Further we discuss about how it can be combined with few other low power techniques to reduce the overall power
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
This paper focuses on the verification challenges and the methodology used to verify a low power design that embeds a combination of techniques to save power.
Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers require these tools and software and it would be an expensive proposition for IP developers.