PCIe Multi-Function Option for DMA IP Cores

The PCI Express specification allows endpoints that incorporate several physical PCIe functions that share the same PCIe connection. Such endpoints are called multi-function devices. The big advantage of a multi-function device is, that a separate device driver can be associated to each physical function. This simplifies driver development and maintenance significantly by separating the peripheral functions logically into different device drivers.

Most FPGA families support multi-function devices but only on a very low level.

This product offers a full-blown multi-function IP core solution with optional DMA support based on our High Channel Count (HCC) IP Core. The core operates with industry standard interfaces (AXI and AXI Stream) and encapsulates the whole PCI Express protocol know-how. This frees the FPGA designer to concentrate on the project specific design tasks.

• Multi-function support with up to 8 PCIe functions.
• Up to 8 AXI Masters to interface user registers
• Up to 16 AXI Stream Slave interfaces
• Up to 16 AXI Stream Master interfaces
• User transmits / receives only user data without PCIe protocol knowledge
• Supports 32-Bit and 64-Bit addressing
• Independent clocking and data width for each AXI Stream interface
• Adjustable priority control
• Memory size up to 4 GByte per streaming channel
• Based on AMD / Altera integrated PCI-Sig compliant PCIe Block (HardIP)
• Link speed Gen 1-4, link widths x1-x8 (depends on the capabilities of the device)
• Available for all AMD and Altera devices