What is ONFI 4.1 I/O Pad Set?
ONFI 4.1 I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
Aragio Solutions
Category:
GPIO
ONFI 4.1 I/O Pad Set
The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage ref…
Overview
The ONFI 4.1 library provides the combo driver / receiver cells, the
ODT / driver impedance calibration cell, and the voltage reference
cell to support both single-ended and differential ONFI 4.1 signaling.
This library also meets the requirements for ONFI 3.0 & Toggle 2.0
signaling. The pad set includes a full complement of power, spacer,
and adapter cells to assemble a complete pad ring by abutment. An
included rail splitter allows isolated ONFI domains to be placed in
the same pad ring with other power domains while maintaining
continuous VDD/VSS in the pad ring for robust ESD protection. Ported from our TSMC 16 silicon proven design.
? ONFI 4.1 Single-Ended Driver /Receiver
? ONFI 4.1 Differential Clock Driver / Receiver
? ODT / ZO Calibration Cell
? Voltage Reference
ODT / driver impedance calibration cell, and the voltage reference
cell to support both single-ended and differential ONFI 4.1 signaling.
This library also meets the requirements for ONFI 3.0 & Toggle 2.0
signaling. The pad set includes a full complement of power, spacer,
and adapter cells to assemble a complete pad ring by abutment. An
included rail splitter allows isolated ONFI domains to be placed in
the same pad ring with other power domains while maintaining
continuous VDD/VSS in the pad ring for robust ESD protection. Ported from our TSMC 16 silicon proven design.
? ONFI 4.1 Single-Ended Driver /Receiver
? ONFI 4.1 Differential Clock Driver / Receiver
? ODT / ZO Calibration Cell
? Voltage Reference
Key features
- ONFI Single-Ended Driver / Receiver Features:
- ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30? / 50? / 75? / 100? / 150?
- o ZOUT = 18? / 25? / 35? / 50?
- o Off state – Z / pull-up / pull-down / bus keeper
- ? Receiver – single-ended and pseudo-differential outputs
- ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
- ? Maximum operating frequency – 400 MHz
- ONFI Differential Clock Driver / Receiver Features:
- ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30? / 50? / 75? / 100? / 150?
- o ZOUT = 18? / 25? / 35? / 50?
- o Off state – Z / pull-up / pull-down / bus keeper
- ? Receiver – single-ended and true differential outputs
- ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
- ? Maximum operating frequency – 400 MHz
What’s Included?
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | Silicon Proven |
Specifications
Identity
Part Number
RGO_TSMC12_18V18_FFC_LL_20C_ONFI_3_4
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about GPIO Pad Library IP cores
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.