What is MPEG TS Deserializer?
MPEG TS Deserializer is a Broadcast IP core from MVD Cores listed on Semi IP Hub.
Vendor:
MVD Cores
Category:
Broadcast
MPEG TS Deserializer
The MVD MPEG TS Deserializer core is a drop-in module that includes the following functions: • Data acquisition on clock • Serial…
Overview
The MVD MPEG TS Deserializer core is a drop-in module that includes the following functions:
• Data acquisition on clock
• Serial/parallel Conversion
• Auto adaptation to 188/204 bytes packet Input
• 188 bytes MPEG-TS output
• No decoding control
• Data acquisition on clock
• Serial/parallel Conversion
• Auto adaptation to 188/204 bytes packet Input
• 188 bytes MPEG-TS output
• No decoding control
Key features
- Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
- Full synthesizable RTL VHDL design (not delivered) for easy customization
Block Diagram
MVD_MPEG-TS_DESERIALIZER block diagram
Applications
- MVD MPEG TS Deserializer may be used in applications related to DVB/MPEG transport streams for Satellite tuner data de-serialization.
What’s Included?
- Datasheet
- Netlist for core generation
- VHDL top file
- VHDL source code : can be delivered as an option under NDA and other specific clauses
Specifications
Identity
Part Number
MVD_MPEG-TS_DESERIALIZER
Vendor
MVD Cores
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
France
Frequently asked questions about broadcast wireless IP cores
How should engineers evaluate this Broadcast?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Broadcast IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.