IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
T2M GmbH
Category:
MIPI PHY
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specific…
Overview
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification are all supported by the MIPI M-PHY Gear 4 IP. a high-bandwidth serial interface technology that can support HS Gear4 rates of up to 11.6Gbps and was specifically designed for mobile applications to achieve reduced pin count and excellent battery efficiency. The UniPro controller and UFS Controller are supported by the RMMI interface compatible MIPI M-PHY Gear 4 IP. The MIPI M-PHY offers reliable embedded system debugging and receiver ocular data monitoring using low-cost Build-In-Self-Test (BIST).
Key features
- Compatible with PCIe base Specification
- Full compatible with PIPE3.0 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
- Support 16-bit/32bit parallel interface
- Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
- Support flexible reference clock frequency
- Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
- Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
- Support programmable transmit amplitude and Deemphasis
- Support TX detect RX function in PCIe Mode
- Support Beacon signal generation and detection in
- Production test support is optimized through high coverage at-speed BIST and loopback
- Integrated on-die termination resistors and IO Pads/Bumps
- Embedded Primary & Secondary ESD Protection
- ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
- Silicon Proven in TSMC 28nm HPC+
Block Diagram
MIPI M-PHY v4.1 IP in 28HPC+ block diagram
Benefits
- RX:DFE+CTLE, TX:2-tap FFE
- Max. Channel Loss:~14dB @6GHz Nyquist
- Low operation current and low standby current
- Competitive IP PPA leading in the market
What’s Included?
- Application Note / User Manual
- Behaviour model, and protected RTL codes
- Protected Post layout netlist and Standard Delay Format (SDF)
- Library (LIB)
- Frame view (LEF)
- Metal GDS (GDSII)
- Test patterns and Test Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 28nm | HPC+ | In Production |
Specifications
Identity
Part Number
MIPI M-PHY v4.1 IP in 28HPC+
Vendor
T2M GmbH
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI M-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
Learn more about MIPI PHY IP core
MIPI DPHY Solution
Infineon Drives Automotive MCU Performance Higher with Synopsys Interface IP
Ron DiGuiseppe, Synopsys
Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
Arif Khan
Super Edge Medical SoC (SEMC)
Post Covid 19, the biggest bet for revival of the industry is on 5G proliferation across the world. It is widely expected that 5G’s Enhanced Mobile broadband (eMMB) with speeds as high as 20X of 4G speed, Ultra reliable and Low Latency Communication ( URLLC) and massive Machine type connectivity (mMTC) will transform the world.
D-PHY, M-PHY & C-PHY? First Look at Testing MIPI's Latest PHY
Chris Loberg, Senior Technical Marketing Manager, Tektronix
Frequently asked questions about MIPI PHY IP
What is MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+?
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+ is a MIPI PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.