MIPI DPHY Bidirectional 4 Lanes - GF 40LP 2.5V

The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for mainstream and FinFET processes, is compliant with the D-PHY specification, operating at 10Gb/s aggregate data rate in 4 lanes. Supporting low-power state modes allows the IP to deliver low-power consumption at the maximum speed to address the energy requirements of battery-operated devices. The D-PHY IP interoperates with the vendor’s CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications. The MIPI D-PHY IP is ASIL B Ready ISO 26262 certified, meeting the stringent requirements of automotive ADAS and Infotainment applications.

• Compliant with the MIPI D-PHY specification, v1.2
• Fully integrated hard macro
• Up to 2.5 Gbps per lane
• Aggregate throughput up to 10 Gbps in 4 data lanes
• Supports PHY Protocol Interface (PPI)
• Low-power escape modes and ultra low-power state modes
• Shutdown mode
• SCAN and loopback BIST modes
• Extensive access to internal programmability registers
• Primary, secondary, TX- and RX-only configurations
• Attachable PLL for primary applications
• Flexible input clock reference
• 50% DDR output clock duty cycle
• Silicon-proven, robust design available in advanced process technologies
• ASIL B Ready ISO 26262 certified for Grade 1 and Grade 2 automotive design