IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
T2M GmbH
Category:
MIPI PHY
MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2.
Overview
The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a RX PHY with one clock lane and 4 data lanes. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. Internal termination resistor with auto-calibration.
Key features
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
- Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
- Supports ultra low power mode, high speed mode and escape mode
- Supports one clock lane and up to four data lanes
- Data lanes support transfer of data in high speed mode
- sequence errors and contentions
- Supports contention detection
- Configurable skew option for each Clock and Data lanes.
- Silicon Proven in TSMC 22ULP
Block Diagram
MIPI D-PHY Rx IP in 22ULP block diagram
Applications
- PC
- Television
- Data storage
- Multimedia Devices
- Recorders
- Mobile devices
What’s Included?
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 22nm | ULP | In Production |
Specifications
Identity
Part Number
MIPI D-PHY Rx IP in 22ULP
Vendor
T2M GmbH
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI D-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
Learn more about MIPI PHY IP core
MIPI DPHY Solution
Infineon Drives Automotive MCU Performance Higher with Synopsys Interface IP
Ron DiGuiseppe, Synopsys
Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
Arif Khan
Super Edge Medical SoC (SEMC)
Post Covid 19, the biggest bet for revival of the industry is on 5G proliferation across the world. It is widely expected that 5G’s Enhanced Mobile broadband (eMMB) with speeds as high as 20X of 4G speed, Ultra reliable and Low Latency Communication ( URLLC) and massive Machine type connectivity (mMTC) will transform the world.
D-PHY, M-PHY & C-PHY? First Look at Testing MIPI's Latest PHY
Chris Loberg, Senior Technical Marketing Manager, Tektronix
Frequently asked questions about MIPI PHY IP
What is MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP?
MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP is a MIPI PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.