Infineon Drives Automotive MCU Performance Higher with Synopsys Interface IP
Ron DiGuiseppe, Synopsys
Vendor:
Synopsys, Inc.
Category:
MIPI PHY
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes - TSMC 12FFC 1.8V, North/South Poly Orientation
The integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors,…
Overview
The integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 6.5Gb/s per lane and 6.5Gs/s per trio respectively for a maximum speed of 44.5Gb/s. The C-PHY/D-PHY addresses energy requirements by supporting low-power state modes and delivering below 1.2pJ/bit at the maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes covering all circuits. The C-PHY/D-PHY IP interoperates with the vendor’s ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications.
Key features
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
- Compliant with the MIPI C-PHY specification, v2.0
- 3 trios in C-PHY mode up to 6.5Gs/s per trio
- Aggregate throughput up to 44.5Gb/s in C-PHY mode and 26Gb/s in D-PHY mode
- Wide PHY Protocol Interface (PPI)
- Low-power escape modes and ultra low-power state modes
- Shutdown mode
- High speed BIST and at-speed scan test
- Primary, secondary, TX- and RX-only configurations
- Flexible input clock reference and lane/trio swap
- Silicon-proven, robust design available in advanced process technologies
Block Diagram
dwc_mipi_cd_tx_2t2l_tsmc12ffc18ns block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | — |
Specifications
Identity
Part Number
dwc_mipi_cd_tx_2t2l_tsmc12ffc18ns
Vendor
Synopsys, Inc.
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI C-PHY
,
MIPI D-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about MIPI PHY IP core
How 8k UHD Displays for Emerging Technologies are Enabled in MIPI DSI
Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach
Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
Discover Synopsys’ first complete UFS 5.0 and M‑PHY v6.0 IP solution for high-speed, efficient storage in mobile, automotive, and AI-enabled systems.
Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
With the rapid development of modern mobile systems there is a great increase in the complexity involved in the IP and SOC designs and correspondingly the functional verification also becomes a challenge. To reduce time to market, IPs needed for the SOC must be developed in parallel to the top level design and should be verified in parallel. This requires strong methodology and infrastructure support which allows the SOC design team to be aligned on the requirements with IP teams. Methodology should also ensure that SOC design team gets the required data for the IP to proceed with the complexity of SOC design.
Frequently asked questions about MIPI PHY IP
What is MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes - TSMC 12FFC 1.8V, North/South Poly Orientation?
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes - TSMC 12FFC 1.8V, North/South Poly Orientation is a MIPI PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.