Vendor: InPsy Category: SRAM

Memory Compiler

Our Memory Compilers offer a comprehensive solution for designers seeking high-density, ultra-high-speed, low-power, and customiz…

Overview

Our Advanced Memory Compilers offer a comprehensive solution for designers seeking high-density, ultra-high-speed, low-power, and customizable memory options. Whether you're developing cutting-edge consumer electronics, high-performance computing systems, IoT devices, or automotive applications, our memory compilers provide the performance, efficiency, and flexibility needed to achieve your design goals.

Key features

  • High-Density Memory Compilers
    • Ideal for applications requiring large amounts of on-chip memory, such as mobile devices, IoT, and embedded systems.
    • SP, 1P, DP, 2P and ROM Compilers
  • Ultra-High-Speed Memory Compilers
    • Engineered for maximum data transfer rates, ensuring fast read/write operations, suitable for high performance computing, AI, and graphics processing applications where speed is critical.
    • SP and Cache Compilers
  • Low-Power Memory Compilers
    • Designed to minimize power consumption without compromising performance, suitable for battery-operated devices and energy-sensitive applications.
    • SP, 1P, DP and 2P Compilers
  • Customized Memory Compilers
    • Tailored configurations to meet specific application needs, including unique power, performance, and area (PPA) requirements. Flexible options for word width, depth, and access time, enabling precise control over memory characteristics.
    • TCAM and multi-port SRAM Compilers
    • Others

Specifications

Identity

Part Number
Memory Compiler
Vendor
InPsy
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

InPsy
HQ: Taiwan (R.O.C.)

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is Memory Compiler?

Memory Compiler is a SRAM IP core from InPsy listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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