What is LRW-AES Core?
LRW-AES Core is a Symmetric Crypto IP core from IP Cores, Inc. listed on Semi IP Hub.
Vendor:
IP Cores, Inc.
Category:
Symmetric Crypto
LRW-AES Core
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-…
Overview
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the new drafts of the P1619 call for a different mode, XTS-AES (see our XTS cores). The LRW1 AES core is tuned for storage applications at the data rates of 3 Gbps and higher. The LRW2 family of cores covers a wide range of area / throughput combinations, allowing the designer to choose the smallest core that satisfies the desired clock/throughput requirements. All LRW cores contain the base AES core AES1 and are available for immediate licensing. LRW3 family is similar to LRW2, but supports 256-bit AES keys and no-penalty key and IV changes.
The design is fully synchronous and available in both source and netlist form.
The design is fully synchronous and available in both source and netlist form.
Key features
- Small size: LRW1 starts at 30,000 ASIC gates at throughput of 12.8 bits per clock
- Synthesized for 600+ MHz clock speeds (70+ Gbps throughput for LRW2-128)
- Completely self-contained: does not require external memory
- Supports Liskov-Rivest-Wagner encryption and decryption (LRW-AES a.k.a. AES-LRW)
- Includes LRW-AES encryption, LRW-AES decryption, key expansion and data interface
- No penalty for key and IV changes (back-to-back operation)
- 128+128 bit LRW keys supported. 256+128 bit key supported by LRW3.
- Easily parallelizable for higher data rates
- Test bench provided
Block Diagram
LRW1 block diagram
Applications
- Storage encryption
What’s Included?
- HDL Source Licenses
- Synthesizable Verilog RTL source code
- Test bench (self-checking)
- LRW-AES vectors for testbenches
- Expected results
- User Documentation
- Netlist Licenses
- Post-synthesis EDIF
- Testbench (self-checking)
- LRW-AES vectors for testbenches
- Expected results
- Place & Route script
Specifications
Identity
Part Number
LRW1
Vendor
IP Cores, Inc.
Type
Silicon IP
Security
Crypto Algorithm
AES
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Frequently asked questions about Symmetric Cryptography IP cores
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.