Vendor: Synopsys, Inc. Category: LPDDR

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5)

The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and…

Controller + PHY + 1 LPDDR5 TSMC 5nm N5FF View all specifications

Overview

The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With multiple
interfaces and supporting a wide frequency range, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 or LPDDR4/4X SDRAMs, precisely targeting specific Power, Performance, and Area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as the following hardened IP components:
A single-bit macrocell (SE slice) for single-ended Command/Address (C/A) and Data (DQ) signals
A single-bit macrocell (DIFF slice) for differential signals (clock signals)
A single-bit macrocell (CMOS slice) for CMOS logic-level based C/A signals
A master macrocell (MASTER)
These macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility
Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the Synopsys LPDDR5/4/4X Universal Memory (uMCTL5) for a complete DDR interface solution.

Key features

  • Low latency, small area, low power
  • Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
  • Compatible with JEDEC standard LPDDR4 and LPDDR4X SDRAMs up to 4267 Mbps
  • DFI 5.0 compliant interface to the memory controller
  • LPDDR5 DFI Frequency Ratio Support: DFI 1:1:4, 1:1:2 modes (DFICLK:CK:WCK)
  • LPDDR4 / LPDDR4X DFI Frequency Ratio Support: DFI 1:2, 1:4 mode support
  • Flexible channel architecture
  • 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels
  • 64-bit support via two 32-bit PHYs or four 16-bit PHYs
  • 1 or 2 memory ranks comprised of x16 and/or x8 (“byte mode”) DRAM devices, including packages using x8 devices on one rank and x16 devices on another
  • Flexible configuration options: up to 2 DQ loads, 8 CA loads, and 4 CS loads
  • Support for many DRAM packaging options:
  • SDRAM components soldered directly to PCB
  • Package on Package PoP devices
  • PHY independent, firmware-based training using an embedded calibration processor
  • Utilizes specialized hardware acceleration engines
  • Automatic periodic retraining through the DFI MASTER Interface
  • Supports:
  • Command Bus Training (VREF and Delay)
  • Write Leveling, Read Gate Training
  • Write/Read Training:
  • Per-bit DQS to DQ centering and per-bit deskew
  • Per-rank VREFDQ training on DRAM DQ bits
  • Periodic retraining for DRAM write (tDQS2DQ) and read (tDQSCK) drift
  • IO calibration and ODT calibration
  • Supports 1 tap of Decision Feedback Equalization
  • Periodic retraining for DRAM write (tDQS2DQ) and read (tDQSCK) drift
  • Read data capture using differential RDQS strobe pair, or, at lower speeds (threshold TBD) using a strobeless CDR-like data capture
  • Support for up to fifteen distinct trained states/frequencies to permit fast frequency changes
  • Each trained state can have unique frequency and I/O drive and ODT impedance settings
  • Three inactive idle states:
  • DFI_LP Mode: most clocks and delay lines gated
  • PHY Inactive: leakage only
  • PHY Retention: Core power removed, most I/Os powered down, SDRAMs held in self-refresh
  • Voltage and temperature compensated delay lines used for:
  • Centering the clock in the address/command window and strobes in the data eyes
  • Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation
  • Only one PLL is required per DDR PHY
  • Support for all write preamble/postamble settings defined by JEDEC
  • SW controllable DQ bit and AC bit swizzling
  • Supports PHYs that go around a die corner and support for both East-West and North-South orientations
  • Includes the PHY Utility Block (PUB)
  • Soft IP Verilog design that includes PHY control features, such as read/write leveling and data eye training
  • APB and JTAG interfaces for register access
  • Test support:
  • At-speed loopback testing on both the address and data channels
  • Delay line BIST
  • MUX-scan ATPG (stuck-at SCAN)
  • PLL lock test
  • ZQ calibration test
  • Facilitates a JTAG register interface for easy test access
  • Firmware-based 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers
  • Direct override programming available for all VREF, ODT, drive strength, and timing delays to facilitate debug and characterization
  • Automotive grade PHYs in development

Benefits

  • Supports JEDEC standard LPDDR5, LPDDR4 and LPDDR4X SDRAMs
  • Support for data rates up to 6400Mbps
  • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory Controller (uMCTL5) for a complete DDR interface solution
  • DFI 5.0 controller interface
  • PHY independent, firmware-based training using an embedded calibration processor
  • Optional dual channel architecture for LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs
  • Support for DFI-based low power modes and lower power sleep and retention modes
  • Support for up to 15 trained states/
  • frequencies with < 5us switching time???
  • Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
  • Built-in anti-aging features to prevent effects of NBTI & HCI

Applications

  • Smartphones and tablets
  • Embedded mobile computing
  • Ultraportable laptops/“Ultrabooks”
  • Automotive
  • Mobile multimedia
  • Digital home/office
  • Wireless connectivity

What’s Included?

  • Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
  • PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
  • Implementation Guide, Application notes, and quick start manuals
  • Firmware for training, ATE test and diagnostics
  • DDR PHY compiler
  • Support for PHY emulation
  • Optional deliverables include:
  • Signal integrity consulting services
  • PHY hardening consulting services
  • Subsystems consulting services
  • IP Prototyping kit for FPGA-based prototyping

Silicon Options

Foundry Node Process Maturity
TSMC 5nm N5FF —

Specifications

Identity

Part Number
dwc_lpddr54_phy_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
LPDDR5

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about LPDDR IP core

Frequently asked questions about LPDDR Interface IP

What is LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5)?

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5) is a LPDDR IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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