Vendor: SmartDV Category: LPDDR

LPDDR2 Assertion IP

LPDDR2 Assertion IP provides an efficient and smart way to verify the LPDDR2 designs quickly without a testbench.

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Overview

LPDDR2 Assertion IP provides an efficient and smart way to verify the LPDDR2 designs quickly without a testbench. The SmartDV's LPDDR2 Assertion IP is fully compliant with standard LPDDR2 Specification.

LPDDR2 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR2 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports LPDDR2 memory devices from all leading vendors.
    • Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F.
    • Supports all the LPDDR2 commands as per the specs.
    • Supports up to 32GB device density
    • Supports the following devices.
    • X8
    • X16
    • X32
    • Supports all speed grades as per specification.
    • Quickly validates the implementation of the LPDDR2 standard JESD209-2E and
    • SD209-2F.
    • Supports Programmable Write latency and Read latency.
    • Supports Programmable burst lengths: 4, 8, and 16.
    • Supports the following Burst Types,
    • Sequential
    • Interleave
    • Checks for following
    • Check-points include power up, initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
    • Supports All Mode registers/Control programming.
    • Supports ZQ/DQ calibration.
    • Supports Overlay window Enable/Disable.
    • Supports Write data Mask.
    • Supports Power Down and Deep Power Down features.
    • Supports Auto Precharge option for each burst access
    • Supports full-timing as well as behavioral versions in one model.
    • Supports all timing delay ranges in one model: min, typical and max.
    • Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
    • Protocol checker fully compliant with LPDDR2 Specification JESD209-2E and JESD209-2F.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPDDR2 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPDDR2 Assertion IP functionality.

Block Diagram

LPDDR2 AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
LPDDR2 AIP
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about LPDDR IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about LPDDR Interface IP

What is LPDDR2 Assertion IP?

LPDDR2 Assertion IP is a LPDDR IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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