LPDDR2 Assertion IP

LPDDR2 Assertion IP provides an efficient and smart way to verify the LPDDR2 designs quickly without a testbench. The SmartDV's LPDDR2 Assertion IP is fully compliant with standard LPDDR2 Specification.

LPDDR2 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR2 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Supports LPDDR2 memory devices from all leading vendors.
• Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F.
• Supports all the LPDDR2 commands as per the specs.
• Supports up to 32GB device density
• Supports the following devices.
• X8
• X16
• X32
• Supports all speed grades as per specification.
• Quickly validates the implementation of the LPDDR2 standard JESD209-2E and
• SD209-2F.
• Supports Programmable Write latency and Read latency.
• Supports Programmable burst lengths: 4, 8, and 16.
• Supports the following Burst Types,
• Sequential
• Interleave
• Checks for following
• Check-points include power up, initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports All Mode registers/Control programming.
• Supports ZQ/DQ calibration.
• Supports Overlay window Enable/Disable.
• Supports Write data Mask.
• Supports Power Down and Deep Power Down features.
• Supports Auto Precharge option for each burst access
• Supports full-timing as well as behavioral versions in one model.
• Supports all timing delay ranges in one model: min, typical and max.
• Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
• Protocol checker fully compliant with LPDDR2 Specification JESD209-2E and JESD209-2F.
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Master mode, Slave mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV LPDDR2 VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure LPDDR2 Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.