LPDDR Synthesizable Transactor

LPDDR Synthesizable Transactor provides a smart way to verify the LPDDR component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR Synthesizable Transactor is fully compliant with standard JESD209B and JESD209A-1 Specification and provides the following features.

• Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1
• Supports all the LPDDR commands as per the specs
• Supports up to 2GB device density
• Supports following devices:
• X16
• X32
• Supports all speed grades as per specification
• Supports programmable CAS latency
• Supports programmable burst lengths: 2,4,8 and 16
• Checks for following:
• Check-points include power up,initialization and power off rules
• State based rules, active command rules
• Read/write command rules etc
• All timing violations
• Supports all mode registers/control programming
• Supports extended mode registers programming
• Supports the following burst types:
• Sequential
• Interleave
• Supports burst order
• Supports write data mask
• Supports power down features
• Supports deep power down features
• Supports auto precharge option for each burst access
• Supports auto refresh and self refresh modes
• Supports full-timing as well as behavioral versions in one model
• Optional partial array self refresh and temperature compensated self refresh
• Model detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the LPDDR testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes