Vendor: T2M GmbH Category: DAC

Low power 8bit 300Ksps R2R Compact area High performance Silicon Proven DAC IP Core

The 8-bit 300 Ksps DAC IP Core employs a high-performance R2R architecture and provides an optional differential current output o…

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Overview

The 8-bit 300 Ksps DAC IP Core employs a high-performance R2R architecture and provides an optional differential current output or differential voltage output. The bandgap and current source are included to provide a complete DAC. The DAC can be configured to adjust full-scale output range and has all the necessary calibration circuitry to provide excellent static and dynamic linearity performance. The DAC uses a proprietary architecture that reduces harmonic and intermodulation distortions at high output frequency and amplitudes. Our data converter (ADC and DAC) IP cores offer sampling rates from a few MSPS to over 20GSPS and resolutions ranging from 6 bits to 14 bits.

Key features

  • 24bit Resolution
  • Upto 300 Ksps Rate
  • Functional from -40 deg C to 125 deg C
  • Reduces noise and power consumption.
  • Provides accurate charge transfer without the need for calibration.
  • Simplifies high-performance analog designs.

Benefits

  • Excellent linearity
  • Compact area
  • High-performance low power
  • Complete subsystem with:
  • Bandgap reference
  • Support for I/Q and array configurations

Applications

  • General purpose software defined radio.
  • High speed data acquisition systems
  • Cellular base station
  • Broadband communications
  • High-speed medical imaging
  • Wideband satellite receiver
  • Wireline Communication
  • Wireless Communication
  • Low Power IoT

What’s Included?

  • CDL netlists
  • Liberty timings
  • Verilog description
  • A full datasheet
  • An integration note.

Specifications

Identity

Part Number
8bit 300Ksps R2R DAC IP Core
Vendor
T2M GmbH
Type
Silicon IP

Analog

Resolution bits
8 Bit

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is Low power 8bit 300Ksps R2R Compact area High performance Silicon Proven DAC IP Core?

Low power 8bit 300Ksps R2R Compact area High performance Silicon Proven DAC IP Core is a DAC IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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