Low-Power 8-bit SAR ADC - 8 bits, 50kSPS, Low Voltage (1.8V), Low Power (20µA) TowerJazz 0.18 um
This macro-cell is a low power, general purpose, 8-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Convert…
Overview
This macro-cell is a low power, general purpose, 8-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) core designed for TowerJazz 0.18μm TS18SL CMOS technology.
The circuit has an internal sample-and-hold circuit and a power-down operation mode to save power in applications where power consumption is critical.
Key features
- 8-bit resolution, 50kSPSspeed
- avdd=1.8V, dvdd=1.8V
- Low power (20µA) inactive mode
- INL=±0.5 LSB, DNL=±0.5LSB
- Power down operation mode
- Indicative area:0.065mm2
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Tower | 180nm | SL | Silicon Proven |
Specifications
Identity
Analog
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about ADC IP cores
What is Low-Power 8-bit SAR ADC - 8 bits, 50kSPS, Low Voltage (1.8V), Low Power (20µA) TowerJazz 0.18 um?
Low-Power 8-bit SAR ADC - 8 bits, 50kSPS, Low Voltage (1.8V), Low Power (20µA) TowerJazz 0.18 um is a ADC IP core from Chipus Microelectronics listed on Semi IP Hub. It is listed with support for tower Silicon Proven.
How should engineers evaluate this ADC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.