Low-leakage LDO in TSMC 40 ULP to supply logic and analog domains (up to 5.5V input supply)
Low-leakage LDO in TSMC 40 ULP to supply logic and analog domains (up to 5.5V input supply) with programmable output voltage from…
Overview
Key features
- Low leakage current for best consumption in sleep mode
- High PSRR to supply analog loads
- Low quiescent
- Support input supply voltage up to 5.5V (Li-Ion, USB)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | ULP | Pre-Silicon |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about LDO Voltage Regulator IP cores
What is Low-leakage LDO in TSMC 40 ULP to supply logic and analog domains (up to 5.5V input supply)?
Low-leakage LDO in TSMC 40 ULP to supply logic and analog domains (up to 5.5V input supply) is a LDO Voltage Regulator IP core from Dolphin Semiconductor listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.
How should engineers evaluate this LDO Voltage Regulator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LDO Voltage Regulator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.