UCIe IP
Welcome to the ultimate UCIe IP hub! Explore our vast directory of UCIe IP.
The UCIe™ physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe™ controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe™ architecture supports multiple standard protocols such as PCIe, CXL and streaming raw mode.
All offers in
UCIe IP
Filter
Compare
11
UCIe IP
from 5 vendors
(1
-
10)
Filter:
- TSMC
- 3nm
-
UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
-
UCIe-S PHY for Standard Package (x32) in TSMC N3P, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
-
UCIe-S PHY for Standard Package (x32) in TSMC N3P, East/West Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
-
UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
-
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
-
Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
-
Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
-
16G UCIe Standard PHY for TSMC 3nm
- 16Gbps per pin and supports 12/8/4Gbps subrates
- High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
-
16G UCIe Advanced PHY for TSMC 3nm
- 16Gbps per pin and supports 12/8/4Gbps subrates
- High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
- BIST features ensure Known Good Die (KGD)
- Sideband for link management and robust training
-
UCIe-S PHY and Controller
- Supports MCM, BGA packages and Chiplet2Chiplet interconnects on PCB
- Available process nodes: 28, 22, 16, 12, 7, 6nm
- X16 and X32 PHY with bump maps defined in UCIe 2.0 specifications
- Industry leading power consumption