UCIe IP

UCIe IP Cores (Universal Chiplet Interconnect Express) facilitate high-bandwidth communication between heterogeneous chiplets, in a single package.

The UCIe™ physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe™ controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe™ architecture supports multiple standard protocols such as PCIe, CXL and streaming raw mode.

Explore our vast directory of UCIe IP Cores below.