IP Catalog > Interface IP Cores > Audio Interface IP > I²S IP Cores

I²S IP Cores

I²S (Inter-IC Sound) IP Cores provide a robust and standardized digital audio interface for transmitting and receiving PCM audio data between integrated circuits in SoC and FPGA-based systems. Designed to implement the I²S protocol as defined by Philips, these IP cores enable seamless communication between audio ADCs, DACs, DSPs, and audio codecs.

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Search (19)
Compare 19 I²S IP Cores from 14 vendors (1 - 10)
  • I2S Controller
    • I²S Controller is designed to transfer audio data to and from Audio codec.
    • It can be configured as both Master and Slave mode using software.
    • The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices.
    Block Diagram -- I2S Controller
  • I2S Verification IP
    • Complies with Philips I2S Specification June 5, 1996
    • Full I2S Transmitter, Receiver and Controller functionality
    • Supports up to 32 channels in transmit path
    • Supports up to 32 channels in receive path
    Block Diagram -- I2S Verification IP
  • I2S Controller IIP
    • Compliant with the Philips I2S Bus Specification
    • Master mode as Controller
    • Slave mode as transmitter and receiver
    • Bidirectional operation through two unidirectional serial data lines
    Block Diagram -- I2S Controller IIP
  • I2S Synthesizable Transactor
    • Supports Philips I2S Bus Specification June 5, 1996
    • Full I2S Transmitter, Receiver and Controller functionality
    • Supports up to 32 channels in transmit path
    • Supports up to 32 channels in receive path
    Block Diagram -- I2S Synthesizable Transactor
  • Simulation VIP for I2S
    • Configurability
    • Fully configurable VIP configuration: Manager/Subordinate, Transmitter/Receiver, Active/Passive
    • Word Length Programmability
    • Supports 8, 12, 16, 20, 24, 32, and user-defined
    Block Diagram -- Simulation VIP for I2S
  • I2S - Ensures proper audio data transmission, synchronization, and integrity
    • I2S (Inter-IC Sound) is a serial bus interface used for connecting digital audio devices. As a Verification IP (VIP), it ensures proper data transmission, signal integrity, timing, and protocol compliance in audio communication systems.
    • This VIP verifies key elements such as word length, frame synchronization, clock behavior, and error handling, making it essential for testing I2S communication in a range of applications, including consumer electronics, automotive, and medical devices
    Block Diagram -- I2S - Ensures proper audio data transmission, synchronization, and integrity
  • I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion
    • The IPB-I2S-TDM-ASRC combines an I2S/TDM configurable serial audio interface with two embedded stereo Asynchronous Sample Rate Converters (ASRCs).
    • The ASRCs can provide very high quality in terms of harmonic distortion and noise, tolerance and rejection of input jitter.
    Block Diagram -- I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion
  • I2S/TDM Multichannel Audio Transceiver
    • The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver.
    • The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging mul-ti-channel audio samples over a configurable number of serial lines (pins).
    Block Diagram -- I2S/TDM Multichannel Audio Transceiver
  • I2S to AHB bridge, following AMBA4 specifications
    • dos_I2S_AHB_bridge is an I2S to AHB bridge, following AMBA4 specifications
  • AXI to I2S Bridge for Audio CODEC
    • dos_axi_i2s_bridge is an AXI to I2S Codec connection. Support for multiple channels.
    • Each channel includes a FIFO accessible from parallel and AXI interfaces.
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