Vendor: SmartDV Category: Test / Debug

IEEE 1149.7 COMPACT TAP IIP

IEEE 1149.7 COMPACT TAP is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant.

Overview

IEEE 1149.7 COMPACT TAP is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant. Through its IEEE 1149.7 COMPACT TAP compatibility,it provides a simple interface to a wide range of low-cost devices. IEEE 1149.7 COMPACT TAP IIP is proven in FPGA environment.The host interface of the IEEE 1149.7 COMPACT TAP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

IEEE 1149.7 COMPACT TAP IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with IEEE 1149.7 standard specification.
  • Supports TAP.7 capability classes T0 to T5.
  • Supports Reset and Selection Unit (RSU) for class T0 optional features.
  • Supports Extended Protocol Unit (EPU) for classes T0 to T3.
  • Supports all mandatory and optional EPU commands.
  • Supports Advanced Protocol Unit (APU) for classes T4 and T5.
  • Supports Transport function with 1 or 2 physical data channels (PDC) each supporting up to 16 data channel clients (DCC).
  • Supports 4 and 2 pin interface as specified in IEEE 1149.7 CJTAG.
  • Supports all mandatory and optional scan formats (JScan, MScan, OScan, and SScan).
  • IEEE 1149.7 Compact TAP supports following scan terminology
    • Data Register Scan.
    • Instruction Register Scan.
    • Control Register Scan.
    • Zero-Bit Scan.
  • IEEE 1149.7 Compact TAP supports following scan topology
    • Series scan topology : Class T0 - T5
    • Star-4 scan topology : Class T3 - T5
    • Star-2 scan topology : Class T4 - T5
  • Can be extended with user defines instructions and registers.
  • Fully synthesizable.
  • Static synchronous design.
  • No internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.

Block Diagram

IEEE 1149.7 COMPACT TAP IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The IEEE 1149.7 COMPACT TAP interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
IEEE 1149.7 COMPACT TAP IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Test / Debug IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about SerDes Test / Debug IP cores

What is IEEE 1149.7 COMPACT TAP IIP?

IEEE 1149.7 COMPACT TAP IIP is a Test / Debug IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP