Overview
The present IP is a Voltage Detector (VDT) circuit. The IP detects the voltage level of input voltage, VIN12, of which the normal operating range is 1.08V~1.32V. When the detected supply voltage (VIN12) increases beyond the detection level (VR12), the corresponding output V12_RY is generated as a high level logic(V33) and V12_RYN as a low level logic, or vice versa, when the detected voltage(VIN12) decreases below the detection level(VF12), the corresponding output V12_RY is generated as a low level logic and V12_RYN is generated as a high level logic.
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