I3C PHY & Controller
DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated …
Overview
DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C bus.
The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.
Key features
Compliant with the following specifications:
- MIPI I3C specification v1.0
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
DTI I3C Controller supports:
- Two wire serial interface up to 12.5 MHz using Push-Pull
- Legacy I2C Device co-existence on the same Bus (with some limitations)
- Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- Legacy I2C messaging
- I2C-like Single Data Rate Messaging (SDR)
- Optional High Data Rate Messaging Modes (HDR-DDR, HDR-TSL, HDR-TSP)
- Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
- Reception of In-band Interrupt Support from the I3C Slave devices
- Reception of Hot-Join from newly added I3C Slave devices
- Synchronous Timing Support and Asynchronous Time Stamping
- Master only operation
- Slave only operation
- Master and slave operation
DTI I3C Master supports:
- Transmission modes: Single Data Rate (SDR) Mode
- Dynamic Address Assignment
- Host-join request
- Secondary master request to be current master
- Slave interrupt request
- Support for I3C common command codes
- Error Detection and Recovery Methods for SDR
DTI I3C Slave supports:
- Transmission modes: Single Data Rate (SDR) Mode
- Dynamic Address Assignment
- Host-join
- In-Band Interrupt
- Error Detection and Recovery Methods for SDR
- Detect HDR Exit Pattern
- Support for I3C common command codes:
- Broadcast CCCs
- RSTDAA
- ENTDAA
- ENEC, DISEC
- ENTAS0, ENTAS1, ENTAS2, ENTAS3
- SETMWL, SETMRL
- Direct CCCs
- SETDASA
- SETNEWDA
- GETSTATUS
- ENEC, DISEC
- ENTAS0, ENTAS1, ENTAS2, ENTAS3
- SETMWL, SETMRL
- GETMWL, GETMRL
- GETMXDS
- GETPID, GETBCR, GETDCR
- GETXTIME
- Broadcast CCCs
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about I2C / I3C IP core
Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
MIPI I3C v1.1 - A Conversation with Ken Foust
How to Connect Sensors with I3C
MIPI CCI over I3C: Faster Camera Control for SoC Architects
Arasan I3C PHY - Ternary vs. Non-Ternary
Frequently asked questions about I2C / I3C IP cores
What is I3C PHY & Controller?
I3C PHY & Controller is a I2C / I3C IP core from Dolphin Technology listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.