Vendor: SmartDV Category: I2C / I3C

I2C/SMBus Synthesizable Transactor

I2C/SMBus Synthesizable Transactor provides an smart way to verify the I2C/SMBus bi-directional two-wire bus.

Overview

I2C/SMBus Synthesizable Transactor provides an smart way to verify the I2C/SMBus bi-directional two-wire bus. The SmartDV's I2C/SMBus Synthesizable Transactor is fully compliant with version 2.1 of the Philip's I2C-Bus Specification and SMBus 2.0 Specification and provides the following features.

Key features

  • Supports standard, fast, and high speed operations
  • Full I2C Master and Slave functionality
  • Supports packet error checking for SMBus mode
  • Supports ARP sequence for SMBus mode
  • Operates as a Master, Slave, or both
  • Monitor, Detects and notifies the testbench of all protocol and timing errors
  • Supports all I2C clocking speeds
  • 7b/10b configurable slave address
  • Compares read data with expected results
  • Bus-accurate timing
  • Various kind of Master and Slave errors generation
  • Supports timeouts forcing and handling in SMBus mode
  • Status counters for various events in bus

Block Diagram

I2C/SMBus Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the I2C/SMBus testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
I2C/SMBus Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about I2C / I3C IP core

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SmartDV Rolls Out Multi-Phase Expansion Plan

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Frequently asked questions about I2C / I3C IP cores

What is I2C/SMBus Synthesizable Transactor?

I2C/SMBus Synthesizable Transactor is a I2C / I3C IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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