I2C Slave Serial Interface Controller

The I2C_SLAVE IP Core is a Philips® I2C compliant slave interface controller. The controller decodes the SCL and SDA bus signals and converts them into a simple series of 8-bit read/write commands for accessing a set of user-defined registers. These registers are defined as either configuration registers or status registers.

Config registers provide general purpose read/write bits for the control of external logic. Status registers are read-only and allow the state of external pins to be monitored via the I2C interface. Both the config and status bits are visible at the controller top-level ports.

The SCL port is an input driven by the I2C Master. The SDA port is connected to a bi-directional tristate buffer. When the I2C controller is inactive, both the SCL and SDA lines will be in a high impedance (high-Z) state.

Note: The SCL and SDA pins should have external (or internal) pullups as per the I2C specification.

• Synthesizable, technology independent IP Core for FPGA and ASIC
• Supplied as human readable VHDL (or Verilog) source code
• Phillips® I2C-bus compliant
• User defined I2C slave address
• Configurable number of 8-bit read/write configuration registers up to a maximum of 128
• Configurable number of 8-bit read-only status registers up to a maximum of 128
• Features standard I2C register addressing common to most I2C peripherals
• Fully configurable clocking allows Standard (100kHz), Fast (400kHz) and custom data rates exceeding 20 MHz
• Compatible with a wide range of I2C master devices such as Micro-controllers and COTs ICs

• I2C slave communication
• Inter-chip board-level communications
• Standard 2-wire comms between a wide range of I2C peripherals, micro-controllers and COTs ICs.