Vendor: SmartDV Technologies Category: I2C / I3C

I2C Assertion IP

I2C Assertion IP provides an efficient and smart way to verify the I2C designs quickly without a testbench.

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Overview

I2C Assertion IP provides an efficient and smart way to verify the I2C designs quickly without a testbench. The SmartDV's I2C Assertion IP is fully compliant with standard I2C Specification.

I2C Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

I2C Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports 6.0 I2C specifications.
    • Start, repeat start and stop for all possible transfers.
    • Supports all I2C clocking speeds including HS mode, Fast mode, Fast mode plus and Ultra-fast mode.
    • 7b/10b configurable Slave address.
    • Allows testing of various bus traffic for Read, Write, General Call and CBUS.
    • Supports complex sequence of 7/10 bit with repeated start command sequences.
    • Supports Bus-accurate timing.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV I2C VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure I2C Assertion IP functionality.

Block Diagram

I2C AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
I2C AIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about I2C / I3C IP cores

What is I2C Assertion IP?

I2C Assertion IP is a I2C / I3C IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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