High-Speed Versatile Core for SHA-3-224/256/384/512 and (c)SHAKE-128/256
XIP3030H is a high-speed IP core designed for versatile support of all variants of the SHA-3 hash function and related extendable…
Overview
XIP3030H is a high-speed IP core designed for versatile support of all variants of the SHA-3 hash function and related extendable-output function SHAKE as well as the SHA-3 derived function cSHAKE and its variants KMAC, TupleHash and ParallelHash (including their arbitrary-length out put variants). SHA-3 and SHAKE are defined in the NIST (National Institute of Standards and Technology) standard FIPS PUB 202 [1] and cSHAKE, KMAC, TupleHash and ParallelHash are spec ified in NIST Special Publication 800-185 [2]. Because of the versatile algorithm support, XIP3030H can be used in various applications that require SHA-3 hashing or other supported SHA-3 based functionalities. XIP3030H is optimized for maximum speed and is optimal for applications that re quire high-speed hashing. SHA-3 plays a central role also in post-quantum cryptography schemes. The design is device-agnostic and fully compliant with various FPGA platforms. XIP3030H offers high level of implementation security and is fully protected against timing attacks as its execution time does not depend on the values of the inputs. The interface of XIP3030H is pin-wise compatible with XIP3030C, the compact versatile SHA-3 core with the same functionalities. The only differences are in performance (latency) and resource requirements.
XIP3030H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3030H does not rely on any FPGA manufacturer-specific features.
Key features
- High Throughput: XIP3030H offers very high throughput with high maximum clock frequency achieving peak throughputs of several tens of Gbps depending on the target high-end FPGA.
- Versatile Algorithm Support: XIP3030H supports SHA-3-224/256/384/512, SHAKE-128/256, cSHAKE-128/256, KMAC, ParallelHash, and TupleHash.
- Secure Architecture: The execution time of XIP3030H is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
- Standard Compliance: XIP3030H is compliant with FIPS 202 and SP 800-185.
- Easy Integration: The 64-bit interface of XIP3030H supports easy integration to various systems.
Block Diagram
Benefits
- Fully digital design
- Portable to any ASIC or FPGA technology
- Fully standard compliant
- Easy to integrate
- Several bus interfaces available
- IP core designed in-house at Xiphera
- Technical support by the original designers and cryptographic experts
- CAVP validated
Applications
- Hash functions are widely used in various applications, for example in verifying the integrity of messages and files, generating and verifying digital signatures, verifying passwords, and also in blockchain technology. Additionally, hash functions are used in cryptographic primitives such as Pseudorandom Number Generators (PRNGs) and Message Authentication Codes (MACs)
What’s Included?
- XIP3030H can be shipped in a number of formats, including netlist, source code, or encrypted source code.
- Additionally, synthesis scripts, a comprehensive testbench, and a detailed datasheet including an integration guide are included.
Specifications
Identity
Security
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Hash / MAC IP cores
What is High-Speed Versatile Core for SHA-3-224/256/384/512 and (c)SHAKE-128/256?
High-Speed Versatile Core for SHA-3-224/256/384/512 and (c)SHAKE-128/256 is a Hash / MAC IP core from Xiphera Ltd listed on Semi IP Hub.
How should engineers evaluate this Hash / MAC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Hash / MAC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.