Overview
NLM (Non Local Mean) is a noise reduction algorithm wherein the value of each pixel is determined a rectangle of pixels around that pixel (a “center patch”) with all identically-sized rectangles of pixels (“search patches”) within a relatively large rectangle around the pixel (the “search window”). A weight is then given to the center pixel of each “search patch” according to the distance of the corresponding search patch from the center patch, and the output pixel is derived by calculating the weighted average of all the pixels in the search window.
This algorithm is relatively complex, requiring a large number of gates. VLSI Plus V-NLM-01 product, however, significantly reduces the number of gates by performing two operations in each clock cycle, keeping an energy efficient architecture where consecutive operations are done on neighboring pixels.
Learn more about Video Processing IP core
The imbalance between I/O speed and internal logic speed in integrated circuits has shifted in recent years in favor of the I/O. While in the past, the performance of integrated circuits was often limited by the I/O rate, today, in both ASICs and FPGAs, internal logic struggles to keep up with the I/O performance.
A two data-lane Serial Video Receiver (SVR), compatible with both MIPI CSI2 and SMIA CCP2 standards, with speeds of up to 2Gbps, is presented.
This paper describes an FPGA-based high-definition video processing platform. The platform supports a wide range of applications including flat-panel TV, projection TV and video monitor.
Configurable Processors for Video Processing SOCs
Programmable FPGA devices are the perfect choice for interfacing with multiple high-resolution image sensors simultaneously...
A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing
