GDDR7 Assertion IP

GDDR7 Assertion IP provides an efficient and smart way to verify the GDDR7 designs quickly without a testbench. The SmartDV's GDDR7 Assertion IP is fully complian with standard GDDR7 Specification.

GDDR7 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR7 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Supports GDDR7 memory devices from all leading vendors.
• Supports 100% of GDDR7 protocol draft JEDEC specification.
• Supports all the GDDR7 commands as per the specs.
• Supports 4 separate independent channels with point-to-point interface for data, address and command.
• Supports command parity
• Supports Double Data Rate (DDR).
• Supports Pseudo channel mode operation.
• Supports 16 - 64 Gbit densities
• Supports X8 mode.
• Supports RDQS mode.
• Supports DQ preamble.
• Supports Bank group features.
• Supports Programmable Read/Write latency.
• Supports Bank grouping and 16 internal banks per channel.
• Supports Data bus inversion (DBI) & Command Address bus inversion (CABI).
• Supports Read/Write data transmission integrity secured by cyclic redundancy check.
• Supports ECC.
• Supports Input/output PLL/DLL on/off mode.
• Supports Read/Write EDC on/off mode.
• Supports Programmable EDC hold pattern for CDR.
• Supports Programmable CRC Read/Write latency.
• Supports Low Power modes.
• Supports Auto refresh & self-refresh modes.
• Supports Command Address, WCK2CK, Read, and Write Training mode’s.
• Supports IEEE.1149.1 boundary scan operation.
• Checks for following
• Check-points include power on, Initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports all mode registers programming.
• Supports for power down features.
• Quickly validates the implementation of the GDDR7 protocol JEDEC draft specification.
• Bus-accurate timing for min, max and typical values.
• Constantly monitors GDDR7 behavior during simulation.
• Protocol checker fully compliant with GDDR7 JEDEC draft specification.
• Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Assertion IP features
• AIP includes:
• System Verilog assertions.
• System Verilog assumptions.
• System Verilog cover properties.
• Synthesizable Verilog Auxiliary code.
• Supports Control mode, Model mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV GDDR7 VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure GDDR7 AIP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.