GDDR6 Controller

High-bandwidth GDDR6 and GDDR6X memory controller delivering 16–21 Gbps per pin over a 32-bit channel, with up to 512 GB/s aggregate bandwidth for multi-channel GPU, AI accelerator, and HPC designs.

The GDDR6 Controller IP is a fully JEDEC-compliant memory controller supporting both GDDR6 (NRZ, up to 16 Gbps/pin) and GDDR6X (PAM4, up to 21 Gbps/pin). Each controller instance manages a ×32-bit channel, with up to 16 instances in parallel achieving 512 GB/s aggregate bandwidth for discrete GPU and AI accelerator ASICs.

The controller implements the full GDDR6 burst protocol, mode register programming, initialization sequence, periodic calibration, and temperature-based refresh — providing a complete memory subsystem for discrete GPU, AI accelerator, and compute ASIC designs.

GDDR6 & GDDR6X

• Single IP supporting both GDDR6 NRZ (16 Gbps) and GDDR6X PAM4 (21 Gbps) pin rates with runtime mode selection for flexible DRAM vendor support.

Multi-Channel Scalability

• Up to 16 independent ×32 channels for 256-bit to 512-bit effective bus width configurations achieving 512 GB/s aggregate bandwidth.

Address Interleaving

• Configurable bank, bank-group, and channel address interleaving for maximizing DRAM efficiency across irregular GPU memory access patterns.

Intelligent Scheduler

• 16-entry read/write queue with bank-group aware scheduling, priority arbitration, and read/write switchover optimisation for GPU memory patterns.

Periodic Calibration

• Background read/write DQ training, ZQ calibration, and VREF adjustment ensuring signal integrity at 16–21 Gbps across temperature and voltage.

Thermal Throttling

• MR4 temperature sensor readout with adaptive bandwidth throttling and refresh scaling to prevent GDDR6 thermal issues during sustained compute.

ECC Support

• Optional 8-bit ECC per 32-bit channel (×32+8 config) for error correction in HPC, automotive AI, and safety-critical GPU deployments.

AXI4 Host Interface

• Wide AXI4 interface (512-bit data per channel) with transaction tracking, QoS priority, and atomic operation support for GPU memory semantics.

PHY Abstraction Layer

• Portable PHY abstraction supporting custom ASIC PHY integration with standard training and calibration interfaces for any process node.

Discrete GPUs

• Gaming and professional GPU ASICs with 12–16 GDDR6/X channels providing 512 GB/s for real-time ray tracing and high-resolution rendering.

AI Training Accelerators

• High-bandwidth memory for AI/ML training chips where GDDR6X provides cost-effective bandwidth for large model weights and gradient storage.

HPC & Scientific

• Scientific computing accelerators for molecular dynamics, CFD, and climate modelling requiring massive memory bandwidth cost-optimised.

Signal Processing

• GDDR6 for radar, SIGINT, and SDR processing ASICs needing sustained 200+ GB/s for real-time FFT and beamforming operations.

Automotive AI Chips

• Level 4/5 autonomous vehicle AI SoCs using GDDR6 for lidar/radar fusion, perception DNNs, and HD map processing.

Vision AI Processors

• Smart camera and video analytics SoCs using GDDR6 as a cost-effective high-bandwidth tier for multi-stream 4K/8K inference.

RTL Source

• GDDR6/6X controller RTL (Verilog)
• PHY abstraction layer
• Calibration and training FSMs
• Parameterised for channels & ECC

Verification Suite

• UVM testbench with GDDR6 model
• JEDEC protocol checker
• Multi-channel coherency tests
• PAM4 signal integrity checks

ASIC Package

• Technology-mapped netlists on request
• Synthesis constraints (SDC)
• PHY integration guide
• Power estimation at target node

Documentation

• Integration guide & register map
• Multi-channel configuration note
• Thermal management application note
• 12-month technical support