GDDR6X Memory Model

GDDR6X Memory Model provides an smart way to verify the GDDR6X component of a SOC or a ASIC. The SmartDV's GDDR6X memory model is fully compliant with GDDR6X draft Specification and provides the following features. Better than Denali Memory Models.

GDDR6X Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR6X Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports GDDR6X memory devices from all leading vendors.
• Supports 100% of GDDR6X protocol draft specification
• Supports all the GDDR6X commands as per the specs.
• Supports 2 separate independent channels with point-to-point interface for data, address and command.
• Supports Double Data Rate (DDR) data.
• Supports up to 8GB device density.
• Supports X8 and X16 Mode.
• Supports PAM4 and RDQS Modes.
• Supports DQ preamble.
• Supports Programmable READ/WRITE latency.
• Supports Bank grouping and 16 internal banks per channel.
• Supports Data bus inversion (DBI) & Command Address bus inversion (CABI).
• Supports Read/Write data transmission integrity secured by cyclic redundancy check.
• Supports WRITE Data mask function (single/double byte mask).
• Supports Programmable EDC hold pattern for CDR.
• Supports Programmable CRC READ/WRITE latency.
• Supports Low Power modes.
• Supports Auto refresh & self-refresh modes.
• Supports On-die termination operation.
• Supports Vendor ID for device identification.
• Supports command address, WCK2CK, read/write training mode’s.
• Supports IEEE.1149.1 boundary scan operation.
• Checks for following
• Check-points include power on, Initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports callbacks for user to get command data on bus.
• Supports all mode registers programming.
• Supports for power down features.
• Quickly validates the implementation of the GDDR6X protocol draft specification.
• Bus-accurate timing for min, max and typical values.
• Constantly monitors GDDR6X behavior during simulation.
• Protocol checker fully compliant with GDDR6X protocol draft specification.
• Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of GDDR6X designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the GDDR6X testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.