GDDR6 Synthesizable Transactor

GDDR6 Synthesizable Transactor provides a smart way to verify the GDDR6 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's GDDR6 Synthesizable Transactor is fully compliant with standard GDDR6 Specification and provides the following features.

• Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12
• Supports all the GDDR6 commands as per the specs
• Supports 2 separate independent channels with point-to-point interface for data, address and command
• Supports double data rate (DDR) or quad data rate (QDR) data
• Supports pseudo channel mode operation
• Supports up to 32GB device density
• Supports X8 and X16 mode
• Supports RDQS mode
• Supports DQ preamble
• Supports bank group features
• Supports programmable read/write latency
• Supports bank grouping and 16 internal banks per channel
• Supports data bus inversion (DBI) & command address bus inversion (CABI)
• Supports read/write data transmission integrity secured by cyclic redundancy check
• Supports input/output PLL/DLL on/off mode
• Supports read/write EDC on/off mode
• Supports write data mask function (single/double byte mask)
• Supports programmable EDC hold pattern for CDR
• Supports programmable CRC READ/WRITE latency
• Supports low power modes
• Supports Refresh Management(RFM)
• Supports auto refresh & self-refresh modes
• Supports on-die termination operation
• Supports vendor ID1 and ID2 for identification
• Supports command address, WCK2CK,read/write training mode’s
• Supports IEEE.1149.1 boundary scan operation
• Supports programmable clock frequency of operation
• Checks for following:
• Check-points include power on, initialization and power off rules
• State based rules, active command rules
• Read/write command rules etc
• All timing violations
• Supports all mode registers programming
• Supports power down features
• Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the GDDR6 testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes