GDDR5 Assertion IP

GDDR5 Assertion IP provides an efficient and smart way to verify the GDDR5 designs quickly without a testbench. The SmartDV's GDDR5 Assertion IP is fully compliant with standard GDDR5 Specifications and provides the following features.

GDDR5 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR5 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Supports GDDR5 memory devices from all leading vendors.
• Supports 100% of GDDR5 protocol standard JESD212C.
• Supports all the GDDR5 commands as per the specs.
• Quickly validates the implementation of the GDDR5 standard JESD212 and JESD212C.
• Supports for programmable clock frequency of operation.
• Supports for all types of timing and protocol violation detection.
• Supports up to 8GB device density.
• Supports the following device modes.
• X16
• X32
• Supports for All Mode register programming.
• Checks for following
• Check-points include power on, Initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports for Single ended interface for command, address and data.
• Supports Double Data Rate (DDR) data (WCK).
• Supports Single Data Rate (SDR) command (CK).
• Supports Double Data Rate (DDR) addressing (CK).
• Supports for Programmable Burst length 8.
• Supports for Programmable read latency and write latency.
• Supports for Write data mask function via address bus.
• Supports for Data bus inversion (DBI) & address bus inversion (ABI).
• Supports for Address training.
• Supports for cyclic redundancy check (CRC-8).
• Supports for Programmable CRC read latency, write latency.
• Supports for Low Power modes.
• Supports for Auto & self-refresh modes.
• Supports for Auto Precharge option for each burst access.
• Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Protocol checker fully compliant with GDDR5 Specification JESD212 and JESD212C.
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Master mode, Slave mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV GDDR5 VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure GDDR5 Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.