GDDR3L Controller IIP

GDDR3L interface provides full support for the GDDR3L interface, compatible with GDDR3L specification and DFI-version 4.0 or 5.0 Specification Compliant. Through its GDDR3L compatibility, it provides a simple interface to a wide range of low-cost devices. GDDR3L IIP is proven in FPGA environment. The host interface of the GDDR3L can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

GDDR3L Controller IIP is supported natively in Verilog and VHDL

• Supports GDDR3L protocol standard GDDR3L Specification.
• Compliant with DFI-version 4.0 or 5.0 Specification.
• Supports all the GDDR3L commands as per the specs.
• Supports up to 16 AXI ports with data width upto 512 bits.
• Supports controllable outstanding transactions for AXI write and read channels
• Supports in port arbitration and multi port arbitration.
• Supports user programmable page policy.
• Closed page policy
• Open page policy
• Supports Error Checking and correction (ECC).
• Supports retry on ECC error, with retry limit user controllable.
• Supports high clock speeds in ASIC and FPGA.
• Supports low latency for write and read path.
• Supports reordering of transactions for higher performance.
• Supports for programmable clock frequency of operation.
• Supports for all types of timing and protocol violation detection.
• Supports for All Mode registers programming.
• Supports for 8 bank operation.
• Supports for Nominal and dynamic on-die termination (ODT) for data,strobe and mask signals.
• Supports for Bidirectional differential data strobe.
• Supports for Programmable Burst length:4,8.
• Supports for Programmable sequential/interleave burst mode.
• Supports for Programmable CAS Read latency.
• Supports for Programmable CAS Write latency.
• Supports for Selectable BC4 or BL8 on-the-fly (OTF).
• Supports for Self refresh mode.
• Supports for Automatic self refresh (ASR).
• Supports for Write leveling.
• Supports for Multipurpose register.
• Supports for Write data mask function.
• Supports for Output driver calibration.
• Supports for On-die termination (ODT).
• Supports for input clock stop and frequency change.
• Fully synthesizable
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The GDDR3L interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis, Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User's Guide and Release notes.