UMC IP Cores

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.

• UMC
• 55nm
• ULP
• Silicon Proven

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias.

• UMC
• 55nm
• ULP
• Silicon Proven

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60).

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library

• UMC
• 55nm
• Silicon Proven

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

• UMC
• 55nm
• Silicon Proven

UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library

• UMC
• 55nm
• Silicon Proven

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

• UMC
• 28nm
• HPC
• Pre-Silicon

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

• UMC
• 28nm
• HPC
• Pre-Silicon

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

• UMC
• 28nm
• HPC
• Pre-Silicon

UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library

• UMC
• 55nm
• Silicon Proven

UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library

• UMC
• 55nm
• Silicon Proven

UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library

• UMC
• 55nm
• Silicon Proven

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias.

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.

• UMC
• 55nm
• ULP
• Pre-Silicon

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias.

• UMC
• 55nm
• ULP
• Silicon Proven