RC Oscillator IP, Output: 50MHz / 70MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency selected 50MHz/70MHz.
- UMC
- 180nm
- G
RC Oscillator IP, Output: 50MHz / 70MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency selected 50MHz/70MHz.
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller u…
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller…
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Enhance…
Band Gap IP, Input: 1.08V - 1.32V, VBG=0.6V, UMC 90nm LL process
Input 1.08V-1.32V, VBG=0.6V, Band Gap, LL process, UMC 90 nm LL Logic/RVT Low-K process.
Band Gap IP, Input: 0.9V - 1.1V, VBG=0.5V, UMC 90nm SP process
Input 0.9V-1.1V, VBG=0.5V, Band Gap, UMC 90nm SP/RVT Logic Low-K process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 90nm SP process
Input 2.25V-2.75V, VBG=1.23V, Bnad Gap, SP process, UMC 90nm SP/RVT (FSG) Logic process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 65nm SP process
Input 2.25V-2.75V, VBG=1.23V, Band Gap, SP process, UMC 65nm SP/RVT Low-K Logic process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 55nm SP process
Input 2.25V-2.75V, VBG=1.23V, Band Gap, SP process, UMC 55nm SP/RVT Low-K Logic process.
Band Gap IP, Input: 2.0V - 4.0V, VBG=1.23V, UMC 0.18um G2 process
Input power range = 2.0V-4.0V, VBG=1.23V, bandgap, UMC 0.18um GII Logic process.
Band Gap IP, Input: 1V - 1.5V, VBG=0.8V, UMC 0.11um HS/AE process
Input 1V-1.5V, VBG=0.8V bandgap, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Band Gap IP, Input: 1V - 1.5V, VBG=0.8V, UMC 0.11um HS/FSG process
Input 1V-1.5V, VBG=0.8V bandgap, UMC 0.11um HS/FSG Logic process.
D/A Converter IP, 10 bits, 80MHz, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process 10-Bit 80MHz 2-channel Digital-to-Analog converter.
D/A Converter IP, 10 bits, RGB channels (3 - ch), 150Msps, current Output, UMC 90nm SP process
10-Bit 150MSPS 3-channel current output Digital-to-Analog converter, UMC 90nm SP/RVT Low-K Logic process.
D/A Converter IP, 12 bits, 80Msps, I-Q channels, UMC 55nm SP process
80MHz 2-chanel Digital-to-Analog converter, UMC 55nm SP/RVT Low-K Logic process.