UMC IP Cores

UMC 65nm 1.0V SP Low-K Logic process synchronous high density Dual Port SRAM compiler (with row redundancy option).

• UMC
• 65nm

UMC 55nm SP Low-K Logic process synchronous Dual Port RAM memory compiler.

• UMC
• 55nm
• SP

UMC 55nm 1.0V Standard Performance (SP) Low-K Logic process synchronous, high density, Dual Port SRAM with row redundancy option.

• UMC
• 55nm
• SP

UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler with redundancy.

• UMC
• 55nm
• SP

UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler.

• UMC
• 55nm
• SP

UMC 0.18um MM/RF process synchronous high density Dual Port SRAM memory compiler.

• UMC
• 180nm
• MS

UMC 0.11um HS/RVT Logic process synchronous high density Dual Port SRAM memory compiler.

• UMC
• 110nm
• HS

UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Dual Port SRAM memory compiler.

• UMC
• 110nm
• LL

UMC 0.11um HS/AE Logic process synchronous High-density Dual Port SRAM memory compiler.

• UMC
• 110nm
• HS

2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process.

• UMC
• 90nm
• SP

Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 130nm
• SP

2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process.

• UMC
• 130nm
• SP

2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process.

• UMC
• 130nm
• SP

LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 180nm

Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• LL

2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process.

• UMC
• 55nm
• SP

DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP

2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process.

• UMC
• 90nm
• SP

LVDS TX Pad, UMC 0.35um Logic process.

• UMC
• 90nm
• SP

8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process.

• UMC
• 130nm
• HS