DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 55nm SP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 55nm SP/RVT Low-K Logic process.
DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 55nm LP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 55nm LP/RVT Low-K Logic process.
DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 40nm LP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 40nm LP/RVT Low-K Logic process.
DLL (All Digital) IP, Input: 200MHz - 533MHz, Output: 200MHz - 533MHz, UMC 65nm LP process
Input 200M-533MHz, output 200M-533MHz, all digital DLL with two-channel DQS delay range, UMC 65nm LP/RVT Low-K Logic process.
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic proc…
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (…
DLL IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF, …
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process.
DLL IP, Input: 18MHz - 45MHz, Output: 18 - 45MHz, UMC 90nm SP process
Input 18M-45MHz, output 18M-45MHz, timing generator DLL, UMC 90nm SP/RVT Low-K process.
DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 0.11um HS/FSG process
Input 100M~400MHz, Output 100M~400MHz DLL-based cell that generates two-channel DQS with 25% timing delay, UMC 0.11um HS/RVT Logi…
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 40nm LP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Pulse Width Modulator, UMC 40nm Logic LP/RVT Low-K process.
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 0.11um HS/AE process
3V~3.6V to 5V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Enhancement) Logic process.
DC-DC IP, Input: 0.95V - 1.5V, Output: 3V/100mA, UMC 0.11um HS/AE process
0.95V~1.5V to 3.0V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Enhancement) Logic process.
DC-DC IP, Input: 5V, Output: 3.3V/300mA, UMC 0.11um HS/AE process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.11um 1.2V/3.3V HS/AE (AL Enhancement) L…
DC-DC IP, Input: 2.5V / 3.3V, Output: 1.05V/250mA, UMC 0.11um HS/AE process
2.5V/3.3V to 1.05V high efficiency converter with 250mA driving capability, compensation built-in, PWM regulator, UMC 0.11um HS/A…
D/A Converter IP, 18 bits, 48KHz, UMC 0.11um HS/AE process
18-Bit 48KHz Sampled Stereo Audio Digital-to-Analog converter with Headphone Driver, UMC 0.11um HS/AE (AL Enhancement) Logic proc…
D/A Converter IP, 18 bits, 48KHz, UMC 0.11um HS/AE process
18-Bit 48KHz Sampled Stereo Audio Digital-to-Analog converter with Headphone Driver, UMC 0.11 um HS/AE (AL Enhancement) Logic pro…
D/A Converter IP, 24 bits, 96KHz, UMC 55nm SP process
24-Bit 96KHz Audio Codec, UMC 55nm SP/RVT 2.5OD3.3 Logic process.
D/A Converter IP, 24 bits, 96KHz, UMC 0.11um HS/AE process
24-Bit 96KHz Sampled Stereo Digital-to-Analog converter Audio CODEC with Headphone Driver and Mono 5V Speaker Amplifier, UMC 0.11…