UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)
- UMC
- 28nm
- HPC
- Pre-Silicon
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)
UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library
UMC 28nm HPM/LVT Logic Process 12-track powerslash_core library
UMC 28nm HPM/LVT Logic Process 12-track powerslash_core library
UMC 28nm HPM/HVT Logic Process 12-track powerslash_core library (C35)
UMC 28nm HPM/HVT Logic Process 12-track powerslash_core library (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)
UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library
UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library
UMC 55nm eFlash/HVT Logic Process High Speed 12-track PowerSlash Kit cell library
UMC 55nm eFlash/HVT Logic Process High Speed 12-track PowerSlash Kit cell library
UMC 28nm HPM/RVT Logic Process 9-track Standard generic core cell library (C38)
UMC 28nm HPM/RVT Logic Process 9-track Standard generic core cell library (C38)
UMC 28nm HPM/RVT 9-track generic core cells(35nm)
UMC 28nm HPM/RVT 9-track generic core cells(35nm)