Embedded EEPROM IP, 64x8 bits for 5V BCD
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers.
- UMC
- 180nm
- BCD
- In Production
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
Embedded EEPROM IP, 64x8 bits for 5V BCD
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers.
Embedded EEPROM IP, 64x8 bits for 5V/18V BCD
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers.
Embedded EEPROM IP, 64x8 bits for 5V/18V BCD
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers.
Embedded MTP (Multi-Time Programmable) IP,1x64 bits for 1.8V/5.5V/+-16V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,32x16 bits for 1.8V/5.5V/+-16V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,32x16 bits for 1.5V/5.5V/+-16V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded OTP (One-Time Programmable) IP, 2Kx8 bits for 1.8V/5.5V/+-16V HV
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 4Kx8 bits for 1.8V/5.5V/+-16V HV
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 64Kx8 bits for 1.2V/3.3V Logic
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 64Kx8 bits for 1.8V/3.3V Logic
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 64Kx8 bits for 1.2V/3.3V Logic_Al
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 128x8 bits for 1.5V/5.5V/+-16V HV
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 512x8 bits for 1.8V/3.3V Logic
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
LogicFlash® Embedded MTP in UMC 180nm~110nm
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UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Process PG Via ROM Compiler
UMC 28nm HPC Process PG Via ROM Compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm ultra low power via1 ROM complier
UMC 40nm ultra low power via1 ROM complier
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias