Band Gap IP, Input: 1.2V - 4V, VBG=0.615V, UMC 0.18um LL process
0.18um, LL, bandgap, VBG=0.615 at VCCAH=1.2V~4V, UMC 0.18um LL Logic process.
- UMC
- 180nm
- LL
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Band Gap IP, Input: 1.2V - 4V, VBG=0.615V, UMC 0.18um LL process
0.18um, LL, bandgap, VBG=0.615 at VCCAH=1.2V~4V, UMC 0.18um LL Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 10MHz - 200MHz, UMC 0.18um G2 process
Input 5M-200MHz, output 10M-200MHz, frequency synthesizable low voltage PLL, UMC 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic proces.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 60MHz - 200MHz, UMC 0.18um G2 process
Input 5M-200MHz, output 60M-200MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
Input 5M-200MHz, output 12.5M-200MHz, frequency synthesizable PLL, UMC 0.18um LL Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process
Input 5M-200MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.15um SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process
Input 5M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.15um SP Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process.
Voltage Detector IP, 4 Levels, UMC 0.13um LL/FSG process
4-level voltage detector, input 1.2V, Ivcca=65uA, UMC 0.13um LL-LVT(FSG) process.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.13um HS/FSG process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.13um HS/FSG Logic process.
Linear Regulator IP, Output: 3.3V/50mA, UMC 0.13um HS/FSG process
3.3V with 50mA driving capability, Istb=70uA Linear Regulator, UMC 0.13um HS/FSG Logic process.
PLL (De-Skew) IP, Input: 15MHz - 110MHz, Output: 15MHz - 110MHz, UMC 0.13um HS/FSG process
Input 15M-110MHz, output 15M-110MHz, De-skew PLL with 0.9V~1.32V power supply range, UMC 0.13um HS/FSG Logic process.
PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process
high speed clock generator using UMC 0.13um 1.2V HS process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Input 10M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um SP/FSG Logic process.
Ring Oscillator IP, Output: 12KHz, UMC 0.13um HS/FSG process
Self-contained ring oscillator, frequency 12KHz.
RC Oscillator IP, Output: 40MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 40MHz.
RC Oscillator IP, Output: 15MHz - 50MHz, UMC 0.13um HS/FSG process
15M~50MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
RC Oscillator IP, Output: 4MHz - 15MHz, UMC 0.13um HS/FSG process
4M~15MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.