Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type, Power On Reset, UMC 0.18um GII Logic process.
- UMC
- 180nm
- G
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type, Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um LL process
Vrr=1.2V Vfr=1.1V, VCC=1.8V, Ivcc=12.2uA, Core type, Power On Reset, UMC 0.18um LL Logic process.
Power on Reset IP, Vrr: 1.2V, Vfr: 1.0V, UMC 0.18um LL process
Vrr=1.2V, Vfr=1.1V, corner type, Power on Reset, UMC 0.18um LL process.
Power on Reset IP, Input: 1.2V, UMC 0.13um SP/FSG process
Vrr=0.76V Vfr=0.66V, input 1.2V, Core type, Power On Reset, UMC 0.13um SP Logic(FSG) process.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=11.7uA, Core type, Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.13um HS/FSG process
0.13um HS process, 3.3V device vcc3I, Vrr=2.2V, Vfr=2V, Ivcc=13mA, Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 2.5V - 3.3V, UMC 0.13um HS/FSG process
2.5V~3.3V POR, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.75V Vfr=0.65V, input 1.2V, Core type, Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.13um HS/FSG process
UMC 0.13um HS Logic process, Vrr=2.2V, without Vfr, A type IO, 3.3V Power On Reset.
Power on Reset IP, UMC 0.11um HS/FSG process
Power on reset(POR) block, UMC 0.11um HS/copper Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.11um HS/AE process
Power on reset(POR) block, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 50MHz - 300MHz, UMC 90nm LL process
Input 5MHz-300MHz, output 50MHz-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process.
PLL (Frequency Synthesizer) IP, Input: 33MHz/66MHz, Output: 1056MHz, UMC 90nm SP process
Input 33MHz/66MHz, output 1056MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 25/50MHz, Output: 400MHz, UMC 90nm SP process
Input 25/50MHz, output 400MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K process.
PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process
This Phase-Locked Loop (PLL) based clock multiplier.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm LL process
Input 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm low leakage (RVT) Low-K process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 20MHz - 300MHz, UMC 90nm SP process
Input 5M-100MHz, output 20M-300MHz, fractional-N frequency synthesizable PLL, UMC 90nm SP/RVT Logic Low-K process.
Input 200M-400MHz, output 800M-1600M 400-800MHz and 200-400MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 50MHz, Output: 667MHz - 1300MHz, UMC 90nm SP process
Input 25M-50MHz, output 667M-1300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL IP, Input: 32.768KHz, Output: 12MHz - 30MHz, UMC 90nm SP process
Input 32.768KHz, output 12M-30MHz, PLL, UMC 90nm SP/RVT Logic Low-K process.