Linear Regulator IP, Input: 4.0V-5.5V, Output: 3.3V / 250mA, 1.8V / 70mA, UMC 0.18um G2 process
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
- UMC
- 180nm
- G
Power management IP cores are essential components in modern SoC and ASIC designs, enabling efficient power regulation, distribution, and energy optimization.
These IP cores include functions such as voltage regulators, DC-DC converters, LDOs, battery management, and power monitoring, ensuring reliable and energy-efficient system operation.
This catalog allows you to compare power management IP cores from leading vendors based on efficiency, power consumption, integration level, and process node compatibility.
Whether you are designing mobile devices, automotive systems, IoT products, or high-performance computing platforms, you can find the right power management IP for your system.
Linear Regulator IP, Input: 4.0V-5.5V, Output: 3.3V / 250mA, 1.8V / 70mA, UMC 0.18um G2 process
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 2.0V-4.0V, Output: 1.8V / 100mA, UMC 0.18um G2 process
3.3V with 100mA driving capability, Istb=100uA Linear Regulator, 0.18um GII Logic process.
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
3.3V with 150mA driving capability, Istb=96uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 60mA, UMC 0.18um G2 process
3.3V with 60mA driving capability, Istb=85uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 240mA, UMC 0.18um G2 process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process.
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0.
Band Gap IP, UMC 0.25um process
VBG=1.23V, VCCA=2.5V, VCCA_min=1.5V, Ivcca=22uA, UMC 0.25um Logic process.
Band Gap IP, Input: 3.3V, VBG=1.23V, UMC 0.13um HS/FSG process
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=23uA, UMC 0.13um HS/FSG Logic process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.2V, UMC 55nm LP process
Input 2.25V-2.75V, VBG=1.2V bandgap, UMC 55nm LP/RVT Logic process.
Band Gap IP, Input: 1.8V, VBG=0.615V, UMC 0.18um G2 process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=30uA, UMC 0.18um GII Logic process.
Band Gap IP, Input: 1.2V, VBG=0.8V, UMC 0.13um HS/FSG process
VBG=0.8V, VCCA=1.2V, VCCA_min=1.0V, Ivcca=47uA, HS process, UMC 0.13um HS/FSG Logic process.
Band Gap IP, Input: 1.0V ~ 2.1V, VBG=0.615V, UMC 0.18um G2 process
UMC 0.18um process 1.8V power supply bandgap reference circuit (layout data base with trimming pad), VBG=0.615V.
Band Gap IP, Input: 3V - 3.6V, VBG=1.22V, UMC 55nm SP process
Input 3V-3.6V, VBG=1.22V, bandgap, UMC 55nm SP/RVT Low-K Logic process.
Band Gap IP, Input: 3.3V, VBG=880.3 mV, UMC 55nm SP process
Power input 3.3V, VBG=880.3 mV bandgap, UMC 55nm SP/RVT Low-K process.
Band Gap IP, Input: 2V - 3.6V, VBG=1.2V, UMC 65nm LP process
Input 2V-3.6V, VBG=1.2V, Band Gap, UMC 65nm LP/RVT Low-K Logic process UHS Library.
Band Gap IP, Input: 2V - 3.6V, VBG=1.23V, UMC 40nm LP process
Input 2V-3.6V, VBG=1.23V bandgap, UMC 40nm LP/RVT Low-K Logic process.
Band Gap IP, Input: 2V - 3.6V, VBG=1.207V, UMC 0.11um HS/AE process
Input 2V-3.6V, VBG=1.207V bandgap, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Band Gap IP, Input: 2V - 3.6V, VBG=1.23V, UMC 90nm SP process
Input 2-3.6V, VBG=1.23V, Bnad Gap, UMC 90nm SP/RVT (FSG) Logic process.