Explore data converter IP cores for mixed-signal SoC, ASIC, and FPGA designs. This category includes a broad range of ADC IP, DAC IP, and Audio Codec IP cores used to bridge the analog and digital domains in embedded, industrial, automotive, consumer, and communications applications.
Data converter intellectual property is essential when a chip needs to sense, digitize, generate, or reconstruct real-world signals. These semiconductor IP blocks are commonly used in sensor interfaces, audio systems, control loops, wireless transceivers, instrumentation, edge AI devices, and power-sensitive embedded platforms.
Browse this category to compare analog and mixed-signal IP by architecture, resolution, sampling rate, power consumption, interface support, process compatibility, and application fit. Whether you need precision conversion, high-speed signal acquisition, or integrated audio conversion, this directory helps you identify the right data converter IP core for your next design.
UMC 40nm high performance mono audio codec with highly integrated analog functionality system
UMC 40nm high performance mono audio codec with integrated analog functionality system
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system
UMC 28nm high performance stereo audio codec with integrated analog functionality system
a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process
10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
UMC 55uLP ADC
A/D Converter IP, 10 bits, 54Msps, Pipelined, Single-end Input, UMC 55nm SP process
1.0V/3.3V 10Bits 54MSPS Single-end Input Pipelined ADC, UMC 55nm SP, LowK, Logic Process
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/FSG process
10bit 1MSPS SAR ADC with 8-to-1 Mux , UMC 0.11um HS/FSG Logic Process