Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
UMC L80G 80nm DDR DLL - 172MHz-860MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
UMC L90SP 90nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90SP 90nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90SP 90nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90GOD 90nm Clock Generator PLL - 125MHz-625MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90GOD 90nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90GOD 90nm Clock Generator PLL - 500MHz-2500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90G 90nm Clock Generator PLL - 90MHz-450MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90G 90nm Clock Generator PLL - 180MHz-900MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L90G 90nm Clock Generator PLL - 360MHz-1800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L80GOD 80nm Clock Generator PLL - 150MHz-750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L80GOD 80nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L80GOD 80nm Clock Generator PLL - 600MHz-3000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L80G 80nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L80G 80nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L80G 80nm Clock Generator PLL - 480MHz-2400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L130SP 130nm Deskew PLL - 59MHz-295MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L130HS 130nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L130HS 130nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
UMC L130HS 130nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…