TSMC CL018E 180nm DDR DLL - 57MHz-285MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CL018E 180nm DDR DLL - 76MHz-380MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CL018G 180nm DDR DLL - 42MHz-210MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CL018G 180nm DDR DLL - 56MHz-280MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CL013LVOD 130nm Spread Spectrum PLL - 440MHz-2200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
TSMC CL013LVOD 130nm Spread Spectrum PLL - 220MHz-1100MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
TSMC CL013LVOD 130nm Spread Spectrum PLL - 110MHz-550MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
TSMC CLN90G 90nm Spread Spectrum PLL - 320MHz-1600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
TSMC CLN90G 90nm Spread Spectrum PLL - 160MHz-800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
TSMC CLN90G 90nm Spread Spectrum PLL - 80MHz-400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
TSMC CL013LVOD 130nm Deskew PLL - 440MHz-2200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013LVOD 130nm Deskew PLL - 220MHz-1100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013LVOD 130nm Deskew PLL - 110MHz-550MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN90G 90nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN90G 90nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN90G 90nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN90G 90nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN90G 90nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL013LVOD 130nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CL013LVOD 130nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.