TSMC CL015G 150nm Clock Generator PLL - 130MHz-650MHz
True Circuits, Inc.
•
HQ:
USA
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 150nm
- G
Compare 3,969 TSMC IP Cores from 81 vendors
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TSMC CL015G 150nm Clock Generator PLL - 65MHz-325MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 150nm
- G
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TSMC CL018E 180nm Clock Generator PLL - 130MHz-650MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 180nm
- E
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TSMC CL015LV 150nm Clock Generator PLL - 70MHz-350MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 150nm
- LV
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TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- G
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TSMC CL013LV 130nm Clock Generator PLL - 320MHz-1600MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV
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TSMC CL013LV 130nm Clock Generator PLL - 80MHz-400MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV
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TSMC CL013LV 130nm Deskew PLL - 80MHz-400MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- LV
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TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- LV
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TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- G
-
TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- G
-
TSMC CL015LV 150nm Deskew PLL - 70MHz-350MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- LV
-
TSMC CL015LV 150nm Deskew PLL - 140MHz-700MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- LV
-
TSMC CL015G 150nm Deskew PLL - 65MHz-325MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- G
-
TSMC CL015G 150nm Deskew PLL - 130MHz-650MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- G
-
TSMC CL018E 180nm Deskew PLL - 65MHz-325MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- E
-
TSMC CL018E 180nm Deskew PLL - 130MHz-650MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- E
-
TSMC CL018G 180nm Deskew PLL - 110MHz-550MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- G
-
TSMC CL018G 180nm Deskew PLL - 55MHz-275MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- G
-
TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV