TSMC IP Cores

This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

• TSMC
• 12nm
• FFC
• Available on request

This TSMC 12nm 0.8V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.

• TSMC
• 12nm
• FFC
• Available on request

This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

• TSMC
• 4nm
• N4AE
• Available on request

This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs.

• TSMC
• 3nm
• N3A
• Available on request

This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm.

• TSMC
• 3nm
• N3A
• Available on request

This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

• TSMC
• 22nm
• ULL
• Available on request